Circuit arrangements for generation of radio frequency output signals which form a broadband frequency ramp are commonly known (see, German Patent Applications DE 10065657 and DE 102004032130, and U.S. Pat. Nos. 5,642,066, and 7,898,344), as well as literature citations “A High Precision 24 GHz FMCW Radar Based on a Fractional-N ramp-PLL”, IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, Vol. 52, No. 2, April 2003, “SiGe Bipolar VCO with Ultra-Wide Tuning Range at 80 GHz Center Frequency”, IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol. 44, No. 10, October 2009).
Circuit arrangements of the type under consideration are used for modem FMCW (frequency modulated continuous wave) radar systems for range finding and velocity measurements with high precision, resolution, and dynamics. The abbreviation FMCW comes from the English term frequency modulated continuous wave (compare Wikipedia “FMCW Radar”).
For FMCW radar systems, circuit arrangements are required in which radio frequency output signals have periodically, linearly rising and/or falling frequencies. The radio frequency output signals of a circuit arrangement of the type under consideration in which frequency output signals have periodically, linearly rising and/or falling frequencies have been designated frequency ramp above and, hereinafter, are also designated frequency ramp.
For applications with high local resolution and good antenna focusing, frequency bands in the millimeter wave range have been standardized in recent years. For automobile applications, the frequency band from 76 GHz to 81 GHz had been released; and, for industrial level measurement, even a 10 GHz wide frequency band from 75 GHz to 85 GHz has been released.
FIG. 1 shows a circuit arrangement of the type under consideration which belongs to the prior art, with a reference oscillator 1, a phase detector 2, a loop filter 3, a voltage-controlled oscillator (i.e., VC oscillator) 4 for generating the radio frequency output signals, a frequency divider 5, and a control unit 6.
FIG. 2a shows the desired linear frequency ramp of the radio frequency output signals as a frequency f of the output signals over a time t. Conversely FIG. 2b shows a typical nonlinear variation of the tuning characteristic of a VC oscillator.
In the circuit arrangement which belongs to the prior art and which is shown in FIG. 1, the reference oscillator 1 is a crystal oscillator and the phase detector 2, the loop filter 3, the VC oscillator 4, the frequency divider 5 and the control unit 6 form a phase-locking loop (i.e., PLL). In the circuit arrangement shown in FIG. 1, a conventional, single-loop PLL is implemented. Assuming stable control with a loop filter 3, the difference phase of the two input signals on the phase detector 2 is adjusted to zero.
The reciprocal value of the division factor will be labeled N below. Therefore the output frequency on the frequency divider 5 corresponds to N-times the input frequency:fA=N·fE 
To generate the frequency ramp, in the simplest case, the frequency divider 5 with each cycle is increased by one value by the control unit 6. A linearized frequency ramp results therefrom by the smoothing lowpass characteristics of the loop filter 3. The use of fractional divider factor sequences also allows variation by rational values and thus enables a further degree of freedom in the choice of the pitch of the frequency ramp and its duration.
The control and stability properties of the above addressed phase-locking loop will be examined using the ring gain.
For the phase detector 2, there is an average output voltage which, with a factor KPD, is proportional to the phase difference of the two input signals, including the input signal coming from the reference oscillator 1 and the input signal coming from the frequency divider 5. The output voltage of the phase detector 2 is filtered in the loop filter 3 and supplied to the VC oscillator 4 as its input voltage. The VC oscillator 4 then delivers radio frequency output signals whose frequency from the input voltage, which corresponds to the output voltage coming from the phase detector 2, filtered by the loop filter 3. The relationship between the input voltage on the VC oscillator 4 and the frequency of the radio frequency output signals of the VC oscillator 4 is shown in FIG. 2b.
The relationship between the input voltage on the VC oscillator 4 and the frequency of the radio frequency output signals of the VC oscillator 4, linearized by a working frequency, can be described by a proportional factor KVCO. For the VC oscillator 4, referenced to its output phase with KVCO/s, an integral behavior arises. If the division factor of the frequency divider 5 in the phase-locking loop, therefore in the feedback path, is added, the ring gain of the entire control circuit is:
            H      ring        ⁡          (      s      )        =            K      PD        ·          F      ⁡              (        s        )              ·                  K        VCO            s        ·                  1        N            .      
In order to be able to also control sudden frequency errors and, thus, linearly rising phase errors, the loop filter 3 must have a largely integral behavior. But, since the phase reserve is already reduced to 90° by the inherent integration of the VC oscillator 4, for the dimensioning of the loop filter 3 at the gain crossover frequency of the ring gain by phase-lifting elements the phase reserve must be increased. In this frequency range then in any case the loop filter 3 deviates from the integral behavior and, as a result of which control is poor, especially noise suppression of the input-side phase noise. For this reason, this frequency range with elevated phase reserve should only limit a narrow range around the gain crossover frequency; this is only possible when the ring gain within the frequency ramp is constant.
If the phase-locking loop is used to generate a frequency ramp by switching the division factor N in the feedback path, this causes a variation of the ring gain. On one hand, the division factor N directly enters into the ring gain, and on the other hand, the altered output frequency causes a change of the tuning steepness of the VC oscillator 4 (compare FIG. 2b). These two effects act unfavorably in the same direction and thus mutually reinforce each other. At low frequencies, the VC oscillator 4 according to FIG. 2b has the highest tuning steepness which is divided by the smallest value of the division factor N. Conversely, at high frequencies, a small tuning steepness is divided by a large division factor N. This can lead to a variation of the ring gain by more than a factor of 10:1.
In general it is possible to dimension the loop filter 3 such that even for a large variation of the ring gain the control is robust, in any case then curtailments must be tolerated in the other control properties, especially in the stabilization of the phase noise near the carrier.
The prior art discloses approaches which keep the ring gain constant by a nonlinear distortion of the input voltage on the VC oscillator 4. This can take place either by digital or analog circuits (see, U.S. Patent Application Publication 2008/0061891 and U.S. Pat. No. 5,642,066), as a result of which almost any nonlinear forms, depending on the selected PLL concept, can be compensated. In any case, very broadband frequency ramps also require VC oscillators with a very large tuning bandwidth, which can only be accomplished by a large tuning steepness. This large tuning steepness causes marginal interferences of the tuning voltage, and of the input voltage on the VC oscillator, like any digital or analog circuit inevitably causes, to induce modulation of the frequency of the radio frequency output signals so that in PLLs for broadband frequency ramps the path from the phase detector 2 to the VC oscillator 4 is very unfavorable for introducing additional circuits.